1. Field of Invention
The present invention relates to a voltage regulator, and more particularly to a voltage regulator for semiconductor memories such as dynamic random access memory (DRAM) and static random access memory (SRAM)
2. Description of Related Art
Along with the rapid development of science and technology at the present, semiconductor memories, as major storage devices for large amount of data are being developed to have larger and larger capacity. As the semiconductor technology is continuously scaled down to achieve high memory density, on-chip voltage regulators providing lower supply voltage for internal circuits are required to fulfill the requirements for device reliability and low power consumption. For DRAM, the bit line sensing, restoring and pre-charge operations in the memory cell arrays consume current abruptly and heavily. For high density DRAM chip, it is challenging to design on-chip voltage regulators for memory cell arrays providing a stable voltage level (Vsa) with sufficient and appropriate supplying current.
FIG. 1 is a circuit diagram of a conventional voltage regulator 100 for DRAM. The voltage regulator 100 includes a differential amplifier unit 11 as a comparator, a feedback unit 12, a PMOS driver transistor mp11, and a NMOS transistor 13.
The differential amplifier unit 11 includes a plurality of transistors 111˜115. NMOS transistor 112 is connected in series with PMOS transistor 114. NMOS transistor 113 is connected in series with PMOS transistor 115. NMOS transistor 111 has its drain connected to the sources of both NMOS transistors 112 and 113, and its source connected to GND. The NMOS transistor 111, which gate is connected to a voltage Vbias1, provides a constant current for the differential amplifier unit 11. The NMOS transistor 112 detects the Vsa1 level from the feedback unit 12 and NMOS transistor 113 receives a reference voltage Vref1. The PMOS transistors 114 and 115, whose gates are connected together, constitute a current mirror. The PMOS transistor 114 has its gate and drain connected together and its source connected to a power supply Vdd. The PMOS transistor 115 is connected between the power supply Vdd and the differential amplifier unit 11 output node. The PMOS driver mp11, whose gate is connected to the differential amplifier unit 11 output, control the currents supplied from the power supply Vdd to the Vsa1 for internal circuit (not shown). The feedback unit 12, having a plurality of resistors R11 and R12, adjusts the ratio of Vsa1 to the reference voltage Vref1. The feedback output voltage Vfb1, is equal to Vsa1*R12/(R11+R12). NMOS transistor 13, normally turned off, is turned on by a rising trigger signal tr1 to pull the gate of PMOS driver transistor mp11 toward ground (GND) and supply more current to Vsa1.
In operation, the differential amplifier unit 11 compares the feedback voltage Vfb1 with a reference voltage Vref1, and then applies the output signal to the gate of PMOS driver transistor mp11 to control the current and regulate the internal power supply Vsa1 for DRAM cell array. If Vsa1 is lower and Vfb1 is less than Vref1, the gate of PMOS driver transistor mp11 will attain toward ground to raise Vsa1. While Vsa1 is getting higher, Vfb1 is rising toward Vref1 and the gate of PMOS driver transistor mp11 will attain toward Vdd to turn off PMOS driver transistor mp11 and stop the Vsa1 rising. In steady state, Vfb1 is equal to Vref1 and Vsa1 is regulated at Vref1*(R11+R12)/R12.
To prevent the excessive drop-down of Vsa1 during bit line sensing, which degrades the DRAM performance, the NMOS transistor 13, turned on and controlled by a trigger signal tr1, pulls down the gate voltage of PMOS driver transistor mp11 toward GND to supply more current and raise the Vsa1 level in advance. This “pre-kick” action prevents some excessive drop-down of Vsa1 voltage at bit line sensing afterwards. Due to lack of a proper feedback mechanism from Vsa1 in controlling the “pre-kick” and slow response of the differential amplifier unit 11, Vsa1 is easier to be raised and dropped excessively.
According to U.S. Pat. No. 6,806,692 B2, a voltage down converter for supplying a voltage and current to semiconductor devices is provided. The voltage down converter resolves several problems of the above conventional voltage regulator 100 for semiconductor memories. However, the voltage down converter, having two amplifiers, is more complex and has higher manufacturing cost.